Yiran Chen, Ph.D.

Electrical and Computer Engineering

John Cocke Distinguished Professor -- [EPONYMOUS]

Yiran Chen, Ph.D. Profile Photo

Research Interests

Emerging memory and storage technologies
Embedded systems, CPS, edge computing, and mobile applications
Neuromorphic computing, deep learning and system security
Low power circuit and system

Bio

Yiran Chen earned his B.S. in 1998 and M.S. in 2001 from Tsinghua University and completed his Ph.D. in 2005 at Purdue University. In 2010, he joined the University of Pittsburgh as an Assistant Professor, where he was later promoted to Associate Professor with tenure in 2014, holding the prestigious Bicentennial Alumni Faculty Fellowship. He currently serves as the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University.

Dr. Chen is the Director of the National Science Foundation (NSF) AI Institute for Edge Computing Leveraging (Athena), one of the 27 National AI Institutes in the United States. He also leads the NSF Industry-University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC) and co-directs the Duke Center for Computational Evolutionary Intelligence (DCEI). His research group focuses on innovations in emerging memory and storage systems, machine learning and neuromorphic computing, and edge computing.

Throughout his career, Dr. Chen has supervised or is currently supervising over 60 Ph.D. students and 4 postdoctoral scholars. Many of his mentees have achieved significant success, with 14 joining faculties at institutions in the United States, Turkey, Hong Kong, and China, including four NSF CAREER Awardees.

Dr. Chen has an extensive publication record, including one book, over 700 technical papers, and 96 U.S. patents. His work has earned 15 paper awards, including two Test-of-Time Awards, and 17 best paper nominations from leading international journals and conferences. Among his numerous accolades, he is one of only three individuals to receive Technical Achievement Awards from both the IEEE Circuits and Systems Society and the IEEE Computer Society, organizations with histories spanning 76 and 79 years, respectively.

He has served as a Distinguished Lecturer for the IEEE Council on Electronic Design Automation (CEDA) and the IEEE Circuits and Systems Society (CASS), as well as a Distinguished Visitor of the IEEE Computer Society (CS). He is a Fellow of the AAAS, ACM, IEEE, and NAI, and a member of the European Academy of Sciences and Arts. From 2021 to 2024, he chaired the ACM Special Interest Group on Design Automation (SIGDA), and he was Editor-in-Chief of the IEEE Circuits and Systems Magazine from 2020 to 2023. Currently, he is the inaugural Editor-in-Chief of the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI) and the inaugural Chair of the IEEE Circuits and Systems Society Machine Learning Circuits and Systems (MLCAS) Technical Committee. He has served as a member of the Committee on Using Machine Learning in Safety-Critical Applications: Setting a Research Agenda, The National Academies of Sciences, Engineering, and Medicine.

Beyond academia, Dr. Chen has contributed to industry as Chairman of the Board, Independent Director, and consultant for several startups and venture capital firms. He is a passionate advocate for the responsible use of AI technologies. Dr. Chen is a founding member of the steering committee for the Academic Alliance on AI Policy (AAAIP) and a Fellow of the Asian American Scholar Forum (AASF).

Education

Ph.D. Purdue University, 2005

Positions

John Cocke Distinguished Professor -- [EPONYMOUS]
Professor in the Department of Electrical and Computer Engineering
Professor of Computer Science

Awards, Honors, and Distinctions

Member. European Academy of Sciences and Arts. 2025
Professional Member . IEEE-Eta Kappa Nu, the Eta Chapter of the Board of Governors. 2025
Inaugural Editor-in-Chief of the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI). IEEE. 2024
Distinguished Visitor. IEEE Computer Society . 2024
Dean's Award for Excellence in Mentoring. Duke University. 2024
Distinguished Lecturer. IEEE Circuits and Systems Society. 2023
Charles A. Desoer Technical Achievement Award. Institute of Electrical and Electronics Engineers (IEEE), Circuits and Systems Society. 2023
Fellow. National Academy of Inventors. 2023
Stansell Family Distinguished Research Award. Pratt School of Engineering, Duke University. 2022
Fellow. American Association for the Advancement of Science. 2022
Edward J. McCluskey Technical Achievement Award. Institute of Electrical and Electronics Engineers (IEEE), Computer Society. 2022
Clarivate Highly Cited Researchers. Clarivate. 2021
Outstanding Electrical and Computer Engineer (OECE) Award. Purdueu2019s School of Electrical and Computer Engineering. 2021
HPCA Hall of Fame. IEEE Computer Society, Technical Committee on Computer Architecture. 2020
Fellow. Association for Computing Machinery. 2020
Fellow. Institute of Electrical and Electronics Engineers. 2018
Distinguished Lecturer. IEEE Council on Electronic Design Automation. 2018
Outstanding New Faculty Award . ACMu2019s Special Interest Group on Design Automation (SIGDA). 2014
National Science Foundation CAREER Awards - Multiple Sciences. National Science Foundation (NSF). 2013

Courses Taught

ECE 899: Special Readings in Electrical Engineering
ECE 891: Internship
ECE 661: Computer Engineering Machine Learning and Deep Neural Nets
ECE 493: Projects in Electrical and Computer Engineering
ECE 392: Projects in Electrical and Computer Engineering
ECE 391: Projects in Electrical and Computer Engineering

Publications

Du H, Zhao Y, Zhao J, Xu S, Lin X, Chen Y, et al. Advancing real-time infectious disease forecasting using large language models. Nature computational science. 2025 Jun;5(6):467u201380.
Pan J, Chang CC, Xie Z, Chen Y, Li H. EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2025.
Kim B, Li S, Taylor B, Chen Y. Efficient and Robust Edge AI: Software, Hardware, and the Co-design. ACM Transactions on Embedded Computing Systems. 2025 Apr 4;24(3).
Chang CC, Ho CT, Li Y, Chen Y, Ren H. DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. In: Proceedings of the International Symposium on Physical Design. 2025. p. 143u201351.
Chang CC, Lin WH, Pan J, Zhou G, Xie Z, Hu J, et al. PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2025. p. 1308u201313.
Pan J, Zhou G, Chang CC, Jacobson I, Hu J, Chen Y. A Survey of Research in Large Language Models for Electronic Design Automation. ACM Transactions on Design Automation of Electronic Systems. 2025 Feb 24;30(3).
Molom-Ochir T, Taylor B, Li H, Chen Y. Advancements in Content-Addressable Memory (CAM) Circuits: State-of-the-Art, Applications, and Future Directions in the AI Domain. IEEE Transactions on Circuits and Systems I Regular Papers. 2025 Jan 1;
Zhang J, Yang H, Li A, Guo X, Wang P, Wang H, et al. MLLM-LLaVA-FL: Multimodal Large Language Model Assisted Federated Learning. In: Proceedings 2025 IEEE Winter Conference on Applications of Computer Vision Wacv 2025. 2025. p. 4066u201376.
Yu F, Xu Z, Shangguan L, Wang D, Stamoulis D, Madhok R, et al. Rethinking Latency-Aware DNN Design With GPU Tail Effect Analysis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2025 Jan 1;44(1):266u201379.
Guo C, Cheng F, Du Z, Kiessling J, Ku J, Li S, et al. A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models. IEEE Circuits and Systems Magazine. 2025 Jan 1;25(1):35u201357.
Wei C, Guo C, Cheng F, Li S, Yang HF, Li HH, et al. Prosperity: Accelerating Spiking Neural Networks via Product Sparsity. In: Proceedings International Symposium on High Performance Computer Architecture. 2025. p. 806u201320.
Sridhar A, Chen Y. Delta-NAS: Difference of Architecture Encoding for Predictor-Based Evolutionary Neural Architecture Search. In: Proceedings 2025 IEEE Winter Conference on Applications of Computer Vision Wacv 2025. 2025. p. 7857u201365.
Kim B, Li HH, Chen Y. Emerging Computing Mechanisms for Edge AI. IEEE Nanotechnology Magazine. 2025 Jan 1;19(2):25u201337.
Kim B, Huang Q, Taylor B, Zheng Q, Ku J, Chen Y, et al. MulPi: A Multi-class and Patient-independent Epileptic Seizure Classifier with Co-designed Input-stationary Computing-in-SRAM. IEEE Transactions on Biomedical Circuits and Systems. 2025 Jan 1;
Sridhar A, Chang CC, Zhang J, Chen Y. Improving Routability Prediction via NAS Using a Smooth One-Shot Augmented Predictor. In: Proceedings International Symposium on Quality Electronic Design Isqed. 2025.
Zhou G, Korrapati B, Reddy GR, Zhang J, Chen Y, Thakurta DG. Vario: Enhance Pattern Diversity with Diffusion Model. In: Proceedings of SPIE the International Society for Optical Engineering. 2025.
Zhang J, Zhou Y, Gu J, Wigington C, Yu T, Chen Y, et al. ARTIST: Improving the Generation of Text-Rich Images with Disentangled Diffusion Models and Large Language Models. In: Proceedings 2025 IEEE Winter Conference on Applications of Computer Vision Wacv 2025. 2025. p. 1268u201378.
Li Y, Sun J, Liu Y, Zhang Y, Li A, Chen B, et al. Federated Black-box Prompt Tuning System for Large Language Models on the Edge. In: ACM Mobicom 2024 Proceedings of the 30th International Conference on Mobile Computing and Networking. 2024. p. 1775u20137.
Zheng Q, Li Z, Ku J, Wang Y, Taylor B, Fan D, et al. Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference. In: Proceedings Design Automation Conference. 2024.
Ku JHC, Zhang J, Shan H, Samudrala S, Wu J, Zheng Q, et al. ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. In: Proceedings Design Automation Conference. 2024.
Chen H, Wang Y, Cargnini V, Soltaniyeh M, Li D, Sun G, et al. ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model. In: Proceedings Design Automation Conference. 2024.
Zhang F, Sridharan A, Tsai W, Chen Y, Wang SX, Fan D. Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning. In: Proceedings Design Automation Conference. 2024.
Roman-Vicharra C, Chen Y, Hu J. Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. In: Mlcad 2024 Proceedings of the 2024 ACM IEEE International Symposium on Machine Learning for CAD. 2024.
Lyu B, Wen S, Yang Y, Chang X, Sun J, Chen Y, et al. Designing Efficient Bit-Level Sparsity-Tolerant Memristive Networks. IEEE transactions on neural networks and learning systems. 2024 Sep;35(9):11979u201388.
Lyu B, Yang Y, Cao Y, Shi T, Chen Y, Huang T, et al. A memristive all-inclusive hypernetwork for parallel analog deployment of full search space architectures. Neural networksu202f: the official journal of the International Neural Network Society. 2024 Jul;175:106312.
Kim B, Li H, Chen Y. Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration. In: Proceedings of the ACM Great Lakes Symposium on VLSI Glsvlsi. 2024. p. 614u20139.
Xu L, Chen Y, Wang Y, Liao N, He J, Wang D. Recognition of Skin Cancer from Dermoscopic Images via DNN. In: ACM International Conference Proceeding Series. 2024. p. 412u20139.
Pan J, Lin X, Xu J, Chen Y, Zhuo C. Lithography Hotspot Detection Based on Heterogeneous Federated Learning With Local Adaptation and Feature Selection. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2024 May 1;43(5):1484u201396.
Li S, Wang Y, Hanson E, Chang A, Seok Ki Y, Li H, et al. NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models. IEEE Transactions on Computers. 2024 May 1;73(5):1248u201361.
Wang D, Wang Y, Yang F, Xu L, Zhang Y, Chen Y, et al. A Soft Sensor with Light and Efficient Multi-scale Feature Method for Multiple Sampling Rates in Industrial Processing. Machine Intelligence Research. 2024 Apr 1;21(2):400u201310.
Wang B, Lin M, Zhou T, Zhou P, Li A, Pang M, et al. Efficient, Direct, and Restricted Black-Box Graph Evasion Attacks to Any-Layer Graph Neural Networks via Influence Function. In: Wsdm 2024 Proceedings of the 17th ACM International Conference on Web Search and Data Mining. 2024. p. 693u2013701.
Yang X, Wang Z, Hu XS, Kim CH, Yu S, Pajic M, et al. Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Transactions on Circuits and Systems II Express Briefs. 2024 Mar 1;71(3):1683u20139.
Chen Y, Banerjee S, Daily S, Krolik J, Li H, Limbrick D, et al. Athena u2013 The NSF AI Institute for Edge Computing. AI Magazine. 2024 Mar 1;45(1):15u201321.
Chang CC, Pan J, Xie Z, Zhang T, Hu J, Chen Y. Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2024 Mar 1;43(3):970u201382.
Inkawhich M, Inkawhich N, Li H, Chen Y. Tunable Hybrid Proposal Networks for the Open World. In: Proceedings 2024 IEEE Winter Conference on Applications of Computer Vision Wacv 2024. 2024. p. 1977u201388.
Samudrala S, Wu J, Chen C, Shan H, Ku J, Chen Y, et al. Performance Analysis of Zero-Knowledge Proofs. In: Proceedings 2024 IEEE International Symposium on Workload Characterization Iiswc 2024. 2024. p. 144u201355.
Duan L, Sun J, Jia J, Chen Y, Gorlatova M. Reimagining Mutual Information for Defense against Data Leakage in Collaborative Inference. In: Advances in Neural Information Processing Systems. 2024.
Chen F, Chen Y. An Interview with Dr. Nicky Lu [Interview]. IEEE Circuits and Systems Magazine. 2024 Jan 1;24(1):6u201312.
Sun J, Xu Z, Yin H, Yang D, Xu D, Liu Y, et al. FedBPT: Efficient Federated Black-box Prompt Tuning for Large Language Models. In: Proceedings of Machine Learning Research. 2024. p. 47159u201373.
Gu J, Vahidian S, Kungurtsev V, Wang H, Jiang W, You Y, et al. Efficient Dataset Distillation via Minimax Diffusion. In: Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition. 2024. p. 15793u2013803.
Yang HF, Zhao Y, Cai J, Zhu M, Hwang JN, Chen Y. Mitigating Bias of Deep Neural Networks for Trustworthy Traffic Perception in Autonomous Systems. In: IEEE Intelligent Vehicles Symposium Proceedings. 2024. p. 633u20138.
Xiao H, Hu X, Gao T, Zhou Y, Duan S, Chen Y. Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits. IEEE Transactions on Circuits and Systems II Express Briefs. 2024 Jan 1;71(1):66u201370.
Chang CC, Shen Y, Fan S, Li J, Zhang S, Cao N, et al. LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits. In: Proceedings of Machine Learning Research. 2024. p. 6253u201362.
Inkawhich M, Inkawhich N, Yang H, Zhang J, Linderman R, Chen Y. OSR-ViT: A Simple and Modular Framework for Open-Set Object Detection and Discovery. In: Proceedings 2024 IEEE International Conference on Big Data Bigdata 2024. 2024. p. 928u201337.
Sun J, Du Z, Dai A, Baghersalimi S, Amirshahi A, Atienza D, et al. PlugVFL: Robust and IP-Protecting Vertical Federated Learning against Unexpected Quitting of Parties. In: Proceedings 2024 IEEE International Conference on Big Data Bigdata 2024. 2024. p. 1124u201333.
Kim B, Huang Q, Taylor B, Zheng Q, Ku J, Ramos N, et al. MulPi: A Multi-Class and Patient-Independent Computing-in-SRAM Seizure Classifier. In: 2024 IEEE Biomedical Circuits and Systems Conference Biocas 2024. 2024.
Zheng Q, Li S, Wang Y, Li Z, Chen Y, Li HL. Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration. In: Proceedings IEEE International Symposium on Circuits and Systems. 2024.
Zhang T, Wen W, Fedorov I, Liu X, Zhang B, Han F, et al. DistDNAS: Search Efficient Feature Interactions within 2 Hours. In: Proceedings 2024 IEEE International Conference on Big Data Bigdata 2024. 2024. p. 1492u20139.
Zhang J, Vahidian S, Kuo M, Li C, Zhang R, Yu T, et al. TOWARDS BUILDING THE FEDERATEDGPT: FEDERATED INSTRUCTION TUNING. In: ICASSP IEEE International Conference on Acoustics Speech and Signal Processing Proceedings. 2024. p. 6915u20139.
Jiang J, Lu H, Liu C, Zhu M, Chen Y, Yang HF. Cost-effective Vehicle Recognition System in Challenging Environment Empowered by Micro-Pulse LiDAR and Edge AI. In: IEEE Intelligent Vehicles Symposium Proceedings. 2024. p. 645u201350.
Zhang T, Li S, Cheng HP, Yan F, Li H, Chen Y. CSCO: Connectivity Search of Convolutional Operators. In: IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. 2024. p. 1685u201394.
Wang Y, Li S, Zheng Q, Song L, Li Z, Chang A, et al. NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing. In: Proceedings International Symposium on Computer Architecture. 2024. p. 368u201381.
Huang Q, Yang H, Zeng E, Chen Y. A Deep-Learning-Based Multi-modal ECG and PCG Processing Framework for Label Efficient Heart Sound Segmentation. In: Proceedings 2024 IEEE ACM Conference on Connected Health Applications Systems and Engineering Technologies Chase 2024. 2024. p. 109u201319.
Wang A, Huang Q, Chen Y. A Quantized Parsimonious CNN Model for Sleep Polysomnogram Data Streams. In: Proceedings 2024 IEEE ACM Conference on Connected Health Applications Systems and Engineering Technologies Chase 2024. 2024. p. 162u20136.
Ibrahim M, Wan Z, Li H, Panda P, Krishna T, Kanerva P, et al. Special Session: Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective. In: Proceedings 2024 International Conference on Hardware Software Codesign and System Synthesis Codes Isss 2024. 2024. p. 11u201320.
Tang M, Sun J, Li HH, Chen Y. Embracing Privacy, Robustness, and Efficiency with Trustworthy Federated Learning on Edge Devices. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi. 2024. p. 284u20139.
Tang M, Dai A, DiValentin L, Ding A, Hass A, Gong NZ, et al. MODELGUARD: Information-Theoretic Defense Against Model Extraction Attacks. In: Proceedings of the 33rd Usenix Security Symposium. 2024. p. 5305u201322.
Zhang J, Juan DC, Rashtchian C, Ferng CS, Jiang H, Chen Y. SLED: Self Logits Evolution Decoding for Improving Factuality in Large Language Models. In: Advances in Neural Information Processing Systems. 2024.
Hanson E, Li S, Zhou G, Cheng F, Wang Y, Bose R, et al. Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AI. In: Proceedings of the 56th Annual IEEE ACM International Symposium on Microarchitecture Micro 2023. 2023. p. 972u201385.
Gao Z, Chen Y, Chen T. Swirls: Sniffing Wi-Fi Using Radios with Low Sampling Rates. In: Proceedings of the International Symposium on Mobile Ad Hoc Networking and Computing Mobihoc. 2023. p. 260u20139.
Wang Y, Li S, Zheng Q, Chang A, Li H, Chen Y. EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference. ACM Transactions on Embedded Computing Systems. 2023 Sep 9;22(5 s).
Li Z, Zheng Q, Chen Y, Li H. SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons. IEEE Transactions on Circuits and Systems II Express Briefs. 2023 Jun 1;70(6):1876u201380.
Zhang T, Cheng D, He Y, Chen Z, Dai X, Xiong L, et al. NASRec: Weight Sharing Neural Architecture Search for Recommender Systems. In: ACM Web Conference 2023 Proceedings of the World Wide Web Conference Www 2023. 2023. p. 1199u2013207.
Xie Z, Pan J, Chang CC, Hu J, Chen Y. The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2023 Apr 1;42(4):1171u201384.
Hanson E, Horton M, Li HH, Chen Y. DefT: Boosting Scalability of Deformable Convolution Operations on GPUs. In: International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS. 2023. p. 134u201346.
Hanson E, Li S, Qian X, Li HH, Chen Y. DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs. IEEE Transactions on Computers. 2023 Mar 1;72(3):880u201392.
Pang M, Wang B, Ye M, Cheung Y-M, Chen Y, Wen B. DisP+V: A Unified Framework for Disentangling Prototype and Variation From Single Sample per Person. IEEE transactions on neural networks and learning systems. 2023 Feb;34(2):867u201381.
Chang CC, Pan J, Xie Z, Hu J, Chen Y. Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2023. p. 252u20137.
Yang X, Li S, Zheng Q, Chen Y. Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2023. p. 618u201323.
Chang CC, Pan J, Xie Z, Li Y, Lin Y, Hu J, et al. Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2023. p. 58u201363.
Zhang J, Wang H, Ravi GS, Chong FT, Han S, Mueller F, et al. DISQ: Dynamic Iteration Skipping for Variational Quantum Algorithms. In: Proceedings 2023 IEEE International Conference on Quantum Computing and Engineering Qce 2023. 2023. p. 1062u201373.
Sun J, Xu Z, Yang D, Nath V, Li W, Zhao C, et al. Communication-Efficient Vertical Federated Learning with Limited Overlapping Samples. In: Proceedings of the IEEE International Conference on Computer Vision. 2023. p. 5180u20139.
Yang Y, Li H, Chen Y. Stable and Causal Inference for Discriminative Self-supervised Deep Visual Representations. In: Proceedings of the IEEE International Conference on Computer Vision. 2023. p. 16063u201374.
Zhang Q, Li S, Zhou G, Pan J, Chang CC, Chen Y, et al. PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2023.
Hu S, Chen Y, Zhu Q, Colombo AW. Guest Editorial Machine Learning for Resilient Industrial Cyber-Physical Systems. IEEE Transactions on Automation Science and Engineering. 2023 Jan 1;20(1):3u20134.
Petri R, Zhang GL, Chen Y, Schlichtmann U, Li B. PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. In: Proceedings Design Automation Conference. 2023.
Gopal B, Sridhar A, Zhang T, Chen Y. LISSNAS: Locality-based Iterative Search Space Shrinkage for Neural Architecture Search. In: Ijcai International Joint Conference on Artificial Intelligence. 2023. p. 773u201381.
Zheng Q, Li S, Wang Y, Li Z, Chen Y, Li HH. Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture. In: Proceedings Design Automation Conference. 2023.
Song L, Chen F, Li H, Chen Y. Refloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers. In: International Conference for High Performance Computing Networking Storage and Analysis Sc. 2023.
Sengupta P, Tyagi A, Chen Y, Hu J. Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction. In: 2023 ACM IEEE 5th Workshop on Machine Learning for CAD Mlcad 2023. 2023.
Zhang J, Inkawhich N, Linderman R, Chen Y, Li H. Mixture Outlier Exposure: Towards Out-of-Distribution Detection in Fine-grained Environments. In: Proceedings 2023 IEEE Winter Conference on Applications of Computer Vision Wacv 2023. 2023. p. 5520u20139.
Xie Z, Pan J, Chang CC, Liang R, Barboza EC, Chen Y. Deep Learning for Routability. In: Machine Learning Applications in Electronic Design Automation. 2023. p. 35u201361.
Wolters C, Taylor B, Hanson E, Yang X, Schlichtmann U, Chen Y. Biologically Plausible Learning on Neuromorphic Hardware Architectures. In: Midwest Symposium on Circuits and Systems. 2023. p. 733u20137.
Linderman R, Zhang J, Inkawhich N, Li H, Chen Y. FINE-GRAIN INFERENCE ON OUT-OF-DISTRIBUTION DATA WITH HIERARCHICAL CLASSIFICATION. In: Proceedings of Machine Learning Research. 2023. p. 162u201383.
Zhang T, Ma M, Yan F, Li H, Chen Y. : Joint Point Interaction-Dimension Search for 3D Point Cloud. In: Proceedings 2023 IEEE Winter Conference on Applications of Computer Vision Wacv 2023. 2023. p. 1298u2013307.
Zhang L, Chen Y, Li A, Wang B, Li F, Cao J, et al. Interpreting Disparate Privacy-Utility Tradeoff in Adversarial Learning via Attribute Correlation. In: Proceedings 2023 IEEE Winter Conference on Applications of Computer Vision Wacv 2023. 2023. p. 4690u20138.
Kim B, Du Z, Sun J, Chen Y. Invited Paper: Towards the Efficiency, Heterogeneity, and Robustness of Edge AI. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2023.
Chen Y. 2023: The Golden Age of Semiconductors. IEEE Circuits and Systems Magazine. 2023 Jan 1;23(1):3.
Zhang J, Muhamed A, Anantharaman A, Wang G, Chen C, Zhong K, et al. ReAugKD: Retrieval-Augmented Knowledge Distillation For Pre-trained Language Models. In: Proceedings of the Annual Meeting of the Association for Computational Linguistics. 2023. p. 1128u201336.
Zhang J, Li A, Tang M, Sun J, Chen X, Zhang F, et al. Fed-CBS: A Heterogeneity-Aware Client Sampling Mechanism for Federated Learning via Class-Imbalance Reduction. In: Proceedings of Machine Learning Research. 2023. p. 41354u201381.
Wu C, Yang X, Chen Y, Li M. Photonic Bayesian Neural Network Using Programmed Optical Noises. IEEE Journal of Selected Topics in Quantum Electronics. 2023 Jan 1;29(2).
Du Z, Sun J, Li A, Chen PY, Zhang J, Li H, et al. Rethinking normalization methods in federated learning. In: Distributedml 2022 Proceedings of the 3rd International Workshop on Distributed Machine Learning Part of Conext 2022. 2022. p. 16u201322.
Zheng Q, Li X, Guan Y, Wang Z, Cai Y, Chen Y, et al. PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2022 Dec 1;41(12):5464u201375.
Liu F, Zhao W, Wang Z, Zhao Y, Yang T, Chen Y, et al. IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2022 Dec 1;41(12):5313u201326.
Li T, Jing N, Jiang J, Wang Q, Mao Z, Chen Y. A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Transactions on Design Automation of Electronic Systems. 2022 Nov 22;27(6).
Chen X, Li D, Chen Y, Xiong J. Boosting the sensing granularity of acoustic signals by exploiting hardware non-linearity. In: Hotnets 2022 Proceedings of the 2022 21st ACM Workshop on Hot Topics in Networks. 2022. p. 53u20139.
Sun J, Li A, Duan L, Alam S, Deng X, Guo X, et al. FedSEA: A Semi-Asynchronous Federated Learning Framework for Extremely Heterogeneous Devices. In: Sensys 2022 Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems. 2022. p. 106u201319.
Xie Z, Liang R, Xu X, Hu J, Chang CC, Pan J, et al. Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2022 Nov 1;41(11):4667u201380.
Chen Y, Qiu Q. Guest Editorial: IEEE TC Special Issue on Software, Hardware and Applications for Neuromorphic Computing. IEEE Transactions on Computers. 2022 Nov 1;71(11):2705u20136.
Pan J, Chang CC, Xie Z, Hu J, Chen Y. Robustify ML-based lithography hotspot detectors. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2022.
Sengupta P, Tyagi A, Chen Y, Hu J. How good is your verilog RTL code? A quick answer from machine learning. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2022.
Xie Z, Li S, Ma M, Chang CC, Pan J, Chen Y, et al. DEEP: Developing extremely efficient runtime on-chip power meters. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2022.
Wang C, Feng D, Tong W, Liu J, Wu B, Chen Y. Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2022 Oct 1;41(10):3479u201391.
Chandra V, Chen Y, Yoo S. Introduction to the Special Section on Energy-Efficient AI Chips. ACM Transactions on Design Automation of Electronic Systems. 2022 Sep 21;27(5).
Zhang J, Tang J, Chen Y, Liu J, Ye J, Wolf M, et al. The 5th Artificial Intelligence of Things (AIoT) Workshop. In: Proceedings of the ACM SIGKDD International Conference on Knowledge Discovery and Data Mining. 2022. p. 4912u20133.
Pan J, Chang CC, Xie Z, Li A, Tang M, Zhang T, et al. Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data. In: Proceedings Design Automation Conference. 2022. p. 961u20136.
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Chen X, Liu B, Chen Y, Zhao M, Xue CJ, Guo X. Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2012. p. 516u201322.
Wang P, Zhang W, Joshi R, Kanj R, Chen Y. A thermal and process variation aware MTJ switching model and its applications in soft error analysis. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2012. p. 720u20137.
Zhou P, Zhao B, Zhang Y, Yang J, Chen Y. MRAC: A memristor-based reconfigurable framework for adaptive cache replacement. In: Parallel Architectures and Compilation Techniques Conference Proceedings Pact. 2011. p. 207u20138.
Zhang Y, Wang X, Chen Y. STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2011. p. 471u20137.
Xue CJ, Zhang Y, Chen Y, Sun G, Yang JJ, Li H. Emerging non-volatile memories: Opportunities and challenges. In: Embedded Systems Week 2011 Esweek 2011 Proceedings of the 9th IEEE ACM IFIP International Conference on Hardware Software Codesign and System Synthesis Codes Isss 11. 2011. p. 325u201334.
Wang P, Chen X, Chen Y, Li H, Kang S, Zhu X, et al. A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. In: Proceedings of the Custom Integrated Circuits Conference. 2011.
Chen Y, Wong WF, Li H, Koh CK. Processor caches built using multi-level spin-transfer torque RAM cells. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2011. p. 73u20138.
Chen YC, Li H, Chen Y, Pino RE. 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. In: Proceedings Design Automation and Test in Europe Date. 2011. p. 583u20136.
Dong X, Wu X, Xie Y, Chen Y, Li H. Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation. IET Computers and Digital Techniques. 2011 May 1;5(3):213u201320.
Hu M, Li H, Chen Y, Wang X, Pino RE. Geometry variations analysis of TiO2 thin-film and spintronic memristors. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2011. p. 25u201330.
Chen Y, Li H. Emerging sensing techniques for emerging memories. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2011. p. 204u201310.
Xu W, Sun H, Wang X, Chen Y, Zhang T. Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration VLSI Systems. 2011 Mar 1;19(3):483u201393.
Zhang Y, Wen W, Chen Y. Asymmetry in STT-RAM cell operations. In: Emerging Memory Technologies Design Architecture and Applications. 2011. p. 117u201344.
Wang P, Wang X, Zhang Y, Li H, Levitan SP, Chen Y. Nonpersistent errors optimization in spin-MOS logic and storage circuitry. IEEE Transactions on Magnetics. 2011 Jan 1;47(10):3860u20133.
Zhu W, Li H, Chen Y, Wang X. Current switching in MgO-based magnetic tunneling junctions. IEEE Transactions on Magnetics. 2011 Jan 1;47(1 PART 2):156u201360.
Li H, Wang X, Ong ZL, Wong WF, Zhang Y, Wang P, et al. Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement. IEEE Transactions on Magnetics. 2011 Jan 1;47(10):2356u20139.
Hu M, Li HH, Chen Y, Wang X. Spintronic memristor: Compact model and statistical analysis. Journal of Low Power Electronics. 2011 Jan 1;7(2):234u201344.
Zhang Y, Wang X, Li H, Chen Y. STT-RAM cell optimization considering MTJ and CMOS variations. IEEE Transactions on Magnetics. 2011 Jan 1;47(10):2962u20135.
Chen Y, Wang X, Li H, Xi H, Yan Y, Zhu W. Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 Dec 1;18(12):1724u201334.
Chen Y, Li H, Wang X, Park J. Applications of TMR devices in solid state circuits and systems. In: 2010 International Soc Design Conference Isocc 2010. 2010. p. 252u20135.
Chen Y, Li H, Wang X. Spintronic devices: From memory to memristor. In: 2010 International Conference on Communications Circuits and Systems Icccas 2010 Proceedings. 2010. p. 811u20136.
Chen Y, Li H, Wang X, Zhu W, Xu W, Zhang T. Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2010. p. 1u20136.
Niu D, Chen Y, Xie Y. Low-power dual-element memristor based memory design. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2010. p. 25u201330.
Li H, Chen Y. Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture. In: Midwest Symposium on Circuits and Systems. 2010. p. 1u20134.
Chen Y, Wang X, Zhu W, Li H, Sun Z, Sun G, et al. Access scheme of multi-level cell spin-transfer torque random access memory and its optimization. In: Midwest Symposium on Circuits and Systems. 2010. p. 1109u201312.
Chen Y, Wang X, Sun Z, Li H. The application of spintronic devices in magnetic bio-sensing. In: Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010. 2010. p. 230u20134.
Niu D, Chen Y, Xu C, Xie Y. Impact of process variations on emerging memristor. In: Proceedings Design Automation Conference. 2010. p. 877u201382.
Chen Y, Tian W, Li H, Wang X, Zhu W. PCMO device with high switching stability. IEEE Electron Device Letters. 2010 Aug 1;31(8):866u20138.
Chen Y, Li H. Patents relevant to cross-point memory array. Recent Patents on Electrical Engineering. 2010 Jun 25;3(2):114u201324.
Wang X, Chen Y. Spintronic memristor devices and application. In: Proceedings Design Automation and Test in Europe Date. 2010. p. 667u201372.
Chen Y, Li H, Wang X, Zhu W, Xu W, Zhang T. A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM). In: Proceedings Design Automation and Test in Europe Date. 2010. p. 148u201353.
Chen Y, Tian W, Li H, Wang X, Zhu W. Scalability of PCMO-based resistive switch device in DSM technologies. In: Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. 2010. p. 327u201332.
Xi H, Stricklin J, Li H, Chen Y, Wang X, Zheng Y, et al. Spin transfer torque memory with thermal assist mechanism: A case study. IEEE Transactions on Magnetics. 2010 Mar 1;46(3 PART 2):860u20135.
Wang X, Chen Y, Gu Y, Li H. Spintronic memristor temperature sensor. IEEE Electron Device Letters. 2010 Jan 1;31(1):20u20132.
Wang X, Chen Y, Zhang T. Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities. In: Analog Circuits and Signal Processing. 2010. p. 253u201394.
Sun Z, Li H, Chen Y, Wang X. Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2010. p. 432u20137.
Chen Y, Li H, Koh CK, Li J, Roy K, Sun G, et al. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration VLSI Systems. 2010 Jan 1;18(11):1621u20134.
Xu W, Zhang T, Chen Y. Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search Speed. IEEE Transactions on Very Large Scale Integration VLSI Systems. 2010 Jan 1;18(1):66u201374.
Wang X, Chen Y. Patents relevant to spintronic memristor. Recent Patents on Electrical Engineering. 2010 Jan 1;3(1):10u20138.
Sun G, Joo Y, Chen Y, Niu D, Xie Y, Li H. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2010.
Koh CK, Wong WF, Chen Y, Li H. The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. In: Proceedings IEEE International Conference on Computer Design VLSI in Computers and Processors. 2009. p. 268u201374.
Chen Y, Li H, Roy K, Koh CK. Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. IEEE Transactions on Very Large Scale Integration VLSI Systems. 2009 Dec 1;17(12):1749u201352.
Chen Y, Wang X. Compact modeling and corner analysis of spintronic memristor. In: 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009. 2009. p. 7u201312.
Li H, Xi H, Chen Y, Stricklin J, Wang X, Zhang T. Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration. In: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2009. 2009. p. 217u201322.
Koh CK, Wong WF, Chen Y, Li H. Tolerating process variations in large, set-associative caches: The buddy cache. Transactions on Architecture and Code Optimization. 2009 Jun 1;6(2).
Xi H, Wang X, Chen Y, Ryan PJ. Ordering of magnetic nanoparticles in bilayer structures. Journal of Physics D: Applied Physics. 2009 Apr 8;42(1).
Wang X, Chen Y, Xi H, Li H, Dimitrov D. Spintronic memristor through spin-thorque-induced magnetization motion. IEEE Electron Device Letters. 2009 Feb 12;30(3):294u20137.
Xu W, Chen Y, Wang X, Zhang T. Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. In: Proceedings Design Automation Conference. 2009. p. 87u201390.
Sun G, Dong X, Xie Y, Li J, Chen Y. A novel architecture of the 3D stacked MRAM L2 Cache for CMPs. In: Proceedings International Symposium on High Performance Computer Architecture. 2009. p. 239u201349.
Xu W, Zhang T, Chen Y. Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. In: Proceedings IEEE International Symposium on Circuits and Systems. 2008. p. 1898u2013901.
Dong X, Wu X, Sun G, Xie Y, Li H, Chen Y. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In: Proceedings Design Automation Conference. 2008. p. 554u20139.
Chen Y, Wang X, Li H, Liu H, Dimitrov DV. Design margin exploration of Spin-Torque Transfer RAM (SPRAM). In: Proceedings of the 9th International Symposium on Quality Electronic Design Isqed 2008. 2008. p. 684u201390.
Wang X, Chen Y, Li H, Dimitrov D, Liu H. Spin torque random access memory down to 22 nm technology. IEEE Transactions on Magnetics. 2008 Jan 1;44(11 PART 2):2479u201382.
Chen Y, Li H, Li J, Koh CK. Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2007. p. 195u2013200.
Wong WF, Kon CK, Chen Y, Li H. VOSCH: Voltage scaled cache hierarchies. In: 2007 IEEE International Conference on Computer Design Iccd 2007. 2007. p. 496u2013503.
Li H, Koh CK, Balakrishnan V, Chen Y. Statistical timing analysis considering spatial correlations. In: Proceedings Eighth International Symposium on Quality Electronic Design Isqed 2007. 2007. p. 102u20137.
Li H, Chen Y, Roy K, Koh CK. SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2006. p. 158u201363.
Chen Y, Li H, Roy K, Koh CK. Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2005. p. 115u20138.
Kang D, Chen Y, Roy K. Power supply noise-aware scheduling and allocation for DSP synthesis. In: Proceedings International Symposium on Quality Electronic Design Isqed. 2005. p. 48u201353.
Chen Y, Roy K, Koh CK. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on Very Large Scale Integration VLSI Systems. 2005 Jan 1;13(1):75u201385.
Lam WCD, Jain J, Koh CK, Balakrishnan V, Chen Y. Statistical based link insertion for robust clock network design. In: IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad. 2005. p. 588u201391.
Chen Y, Li H, Roy K, Koh CK. Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. In: Proceedings of the Custom Integrated Circuits Conference. 2005. p. 775u20138.
Chen Y, Roy K, Koh CK. Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2004. p. 894u20139.
Li H, Bhunia S, Chen Y, Roy K, Vijaykumar TN. DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design. IEEE Transactions on Very Large Scale Integration VLSI Systems. 2004 Mar 1;12(3):245u201354.
Chen Y, Roy K, Koh CK. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229u201334.
Li H, Bhunia S, Chen Y, Vijaykumar TN, Roy K. Deterministic clock gating for microprocessor power reduction. In: Proceedings International Symposium on High Performance Computer Architecture. 2003. p. 113u201322.
Chen Y, Roy K, Koh CK. Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229u201334.
Chen Y, Balakrishnan V, Koh CK, Roy K. Model reduction in the time-domain using Laguerre polynomials and Krylov methods. In: Proceedings Design Automation and Test in Europe Date. 2002. p. 931u20136.

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