Lisa Wills

Research Interests

I enjoy solving difficult problems surrounding computations with the goal to process large volumes of data efficiently. My research interests include computer architecture and microarchitecture, hardware-software co-designs, accelerators, and emerging application domains u2015 especially those in big data analytics such as genomics, graphs, and databases. One of my research goals is to greatly simplify the design, deployment, and usage of custom hardware and to leverage this research in hardware acceleration to advance state-of-the-art research in the healthcare domain as well as other natural sciences.

Education

• Ph.D. Columbia University, 2014

Positions

• Assistant Professor of Computer Science
• Assistant Professor of Electrical and Computer Engineering

Courses Taught

• ECE 891: Internship
• ECE 590: Advanced Topics in Electrical and Computer Engineering
• ECE 557: Computer Architecture and Hardware Acceleration
• ECE 552: Advanced Computer Architecture I
• ECE 494: Projects in Electrical and Computer Engineering
• COMPSCI 590: Advanced Topics in Computer Science
• COMPSCI 557: Computer Architecture and Hardware Acceleration
• COMPSCI 550: Advanced Computer Architecture I
• COMPSCI 210D: Introduction to Computer Systems

Publications

• Wills LW, Tickoo O. Message from Program Chairs. Proceedings - 2024 IEEE International Symposium on Workload Characterization, IISWC 2024. 2024 Jan 1;x.
• Fang W, Lu Y, Liu S, Zhang Q, Xu C, Wills LW, et al. Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024 Jan 1;
• Xu C, Sharma P, Wang T, Wills LW. Fast, Robust and Transferable Prediction for Hardware Logic Synthesis. In: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023. 2023. p. 167u201379.
• Ma J, Xu C, Wills LW. PyTFHE: An End-to-End Compilation and Execution Framework for Fully Homomorphic Encryption Applications. In: Proceedings - 2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023. 2023. p. 24u201334.
• Fang W, Lu Y, Liu S, Zhang Q, Xu C, Wills LW, et al. MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2023.
• Alcorta ES, Gerstlauer A, Deng C, Sun Q, Zhang Z, Xu C, et al. Special Session: Machine Learning for Embedded System Design. In: Proceedings - 2023 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023. 2023. p. 28u201337.
• Xu C, Kjellqvist C, Wills LW. SNS's not a Synthesizer: A Deep-Learning-Based Synthesis Predictor. In: Proceedings - International Symposium on Computer Architecture. 2022. p. 847u201359.
• Robson E, Xu C, Wills LW. Prose: The architecture and design of a protein discovery engine. In: International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2022. p. 655u201368.
• Ang P, Dhingra B, Wills LW. Characterizing the Efficiency vs. Accuracy Trade-off for Long-Context NLP Models. In: NLP-Power 2022 - 1st Workshop on Efficient Benchmarking in NLP, Proceedings of the Workshop. 2022. p. 113u201321.
• Ham TJ, Lee Y, Seo SH, Song UG, Lee JW, Bruns-Smith D, et al. Accelerating Genomic Data Analytics with Composable Hardware Acceleration Framework. IEEE Micro. 2021 May 1;41(3):42u20139.
• Wills LW, Swaminathan K. Guest Editorial: IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications. IEEE Transactions on Computers. 2020 Aug 1;69(8):1096u20138.
• Ham TJ, Bruns-Smith D, Sweeney B, Lee Y, Seo SH, Song UG, et al. Genesis: A Hardware Acceleration Framework for Genomic Data Analysis. In: Proceedings - International Symposium on Computer Architecture. 2020. p. 254u201367.
• Wu L, Bruns-Smith D, Nothaft FA, Huang Q, Karandikar S, Le J, et al. FPGA Accelerated INDEL realignment in the cloud. In: Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. 2019. p. 277u201390.
• Ham TJ, Wu L, Sundaram N, Satish N, Martonosi M. Graphicionado: A high-performance and energy-efficient accelerator for graph analytics. In: Proceedings of the Annual International Symposium on Microarchitecture, MICRO. 2016.
• Wu L, Lottarini A, Paine TK, Kim MA, Ross KA. The Q100 Database Processing Unit. IEEE Micro. 2015 May 1;35(3):34u201346.
• Wu L, Polychroniou O, Barker RJ, Kim MA, Ross KA. Energy analysis of hardware and software range partitioning. ACM Transactions on Computer Systems. 2014 Sep 23;32(3).
• Wu L, Lottarini A, Paine TK, Kim MA, Ross KA. Q100: The architecture and design of a Database Processing Unit. In: International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2014. p. 255u201368.
• Wu L, Barker RJ, Kim MA, Ross KA. Hardware partitioning for big data analytics. IEEE Micro. 2014 Jan 1;34(3):109u201319.
• Wu L, Barker RJ, Kim MA, Ross KA. Navigating big data with high-throughput, energy-efficient data partitioning. In: Proceedings - International Symposium on Computer Architecture. 2013. p. 249u201360.
• Wu L, Kim M, Edwards S. Cache impacts of datatype acceleration. IEEE Computer Architecture Letters. 2012 Jan 1;11(1):21u20134.
• Weaver C, Krishna R, Wu L, Austin T. Application specific architectures: A recipe for fast, flexible and power efficient designs. In: CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2001. p. 181u20135.
• Wu L, Weaver C, Austin T. CryptoManiac. In: Proceedings of the 28th annual international symposium on Computer architecture  - ISCA u201901. ACM Press; 2001. p. 110u20139.
• Wu L, Weaver C, Austin T. CryptoManiac: A fast flexible architecture for secure communication. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 2001 Jan 1;110u20139.

In The News

• New Faculty, Bold Thinking (Oct 15, 2019 | Duke Stories)