Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Andrew Tie

2/26/26 Research

Duke engineers show how a common device architecture used to test 2D transistors overstates up to sixfold their performance prospects in real-world devices.

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Victoria Ravel works in a lab
Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

For nearly two decades, two‑dimensional (2D) semiconductors have been studied as a complement or possible successor to silicon transistors, promising smaller, faster and more energy‑efficient processors.

To ease their production and testing process, much of the field has been benchmarking the potential of 2D semiconductors using an architecture that causes a phenomenon called “contact gating.” Now, findings from electrical engineers at Duke University suggest that this approach inflates how these transistors perform on paper and cannot be translated into commercial technologies.

The research appeared online February 17 in ACS Nano from the lab of Aaron Franklin, the Edmund T. Pratt, Jr. Distinguished Professor of Electrical and Computer Engineering (ECE).

Aaron Franklin
Aaron Franklin

“Most reports of high-performance 2D transistors use a device design that isn’t compatible with commercial technologies,” Franklin said. “What we show is that this design changes how the transistor operates in a way that can significantly inflate performance. If you don’t account for that, it becomes very difficult to fairly evaluate how these materials will behave in a future transistor technology.”

Transistors are the fundamental building blocks of all computers. They rapidly turn electrical currents on and off to form the 1s and 0s used in all programming languages. To improve processing performance, transistors must be made smaller, faster, more efficient—or all three.

Silicon has long been the semiconductor of choice to make transistors, but modern technology is pushing the material’s intrinsic limitations. Already, components found within transistors are as thin as physics will allow. To push beyond these limits, researchers are exploring different materials that can still work even if only one or two atoms thick—so-called 2D materials.

Aaron Franklin

What we show is that this design changes how the transistor operates in a way that can significantly inflate performance. If you don’t account for that, it becomes very difficult to fairly evaluate how these materials will behave in a future transistor technology.

 Aaron Franklin Edmund T. Pratt, Jr. Distinguished Professor of ECE
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To study those materials’ performance, researchers often rely on a simple “back‑gated” architecture that builds all the transistor’s components on a single piece of silicon to make fabrication easier and allow rapid experimentation. In this setup, an ultrathin 2D semiconductor like molybdenum disulfide (MoS₂) sits between two metal contact electrodes that pass current through the semiconductor. The current flow is turned on or off using the silicon substrate as the gate control.

However, the gate doesn’t just modulate the 2D semiconductor channel; in the “back-gate” architecture it also influences the portion of the semiconductor that is below the metal contacts. This creates a phenomenon called “contact gating,” an effect that amplifies the transistor’s performance by lowering contact resistance using the gate.

“Amplifying performance sounds like a good thing,” Franklin said. “But while this architecture is great for basic testing in a lab, it has physical limitations like speed and current leakage that prevent it from being used in an actual device technology.”

Victoria Ravel

With fabrication, you never know what you’re going to run into. When you’re fabricating at such small dimensions, things start to get really difficult with what you’re able to do within physical limits.

 Victoria Ravel PhD Student, Electrical and Computer Engineering
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To reveal this underlying contributing factor that is present in hundreds of laboratory studies on 2D transistors, Victoria Ravel, a PhD student in Franklin’s lab, spent a year fabricating a new device architecture that allows the team to directly measure how much contact gating alters their performance.

She built a symmetric dual-gate transistor, which includes gates above and below the same 2D semiconductor channel, contacts and materials. The only difference between controlling the device with the back or top gate was whether contact gating was present, so she could perform a one-to-one comparison.

Graphics showing the symmetric dual-gate setup. There is a channel flanked by source and drain metals with a top gate and bottom gate. A graph shows improved performance with contact gating.
The symmetric dual-gate transistor built by Ravel allowed her to compare results with and without contact gating.

“With fabrication, you never know what you’re going to run into,” Ravel said. “When you’re fabricating at such small dimensions, things start to get really difficult with what you’re able to do within physical limits.”

The results were striking. In larger devices, contact gating roughly doubled performance. As Ravel scaled devices down to tiny dimensions relevant for future technologies, the contact gating effect increased. At a channel length of 50 nanometers and contact lengths of 30 nanometers, contact gating boosted performance by up to six times.

As devices shrink, Franklin explained, the contacts dominate overall performance. Any mechanism that alters contact behavior becomes increasingly important.Because most 2D transistor results reported over the years have used back‑gated architectures, the findings from Franklin and Ravel have broad implications.

Next, the team plans to push scaling even further, with contact lengths down to 15 nanometers, and investigate alternative contact metals to reduce the contact resistance. The broader goal is to establish clearer design rules for integrating 2D semiconductors into future transistor technologies.

“If 2D materials are going to replace silicon channels someday,” Franklin said, “we need to be honest about how device architecture shapes what we measure. This work is about setting that foundation.”

This research was supported by the National Science Foundation (2227175, 2401367, 2328712, ECCS-2025064).

CITATION: “Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure.” Victoria M. Ravel, Sarah R. Evans, Samantha K. Holmes, James L. Doherty, Md Sazzadur Rahman, Tania Roy, and Aaron D. Franklin. ACS Nano, 2026. DOI: 10.1021/acsnano.5c19797

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