How Duke Engineers Helped Set the Stage for Machine Learning with On-Chip Training
Mixed-signal training acceleration proposed in 2014 wins Yiran Chen a ‘10-year Retrospective’ award
Yiran Chen, the John Cocke Distinguished Professor of Electrical and Computer Engineering, at Duke has won his second “Test of Time” award of the past year for papers whose influence has been recognized as seminal in the field.
The first award recognized a paper proposing a robust memristor—memory resistor—circuit design that could accelerate neural networks. Now, Chen and his co-authors from Tsinghua University have received the 10-Year Retrospective Most Influential Paper Award from ASP-DAC.
The award highlights what was, in 2014, a new methodology for training artificial neural networks on the memristor-based circuitry itself. In combination, the two papers comprised a launchpad for future research in this promising form of artificial intelligence (AI) chips.
At its most basic level, machine learning has two steps. Step one is training the algorithm or giving it a set of parameters to operate from. Step two is inference—arriving at a conclusion after applying the parameters to process an input. And neuromorphic computing seeks to emulate the most efficient of all systems—the human brain—in this process by building artificial neural networks, or ANNs, on hardware.
One problem is that running those ANNs on conventional computers, the design of which is often called von Neumann architecture, is known to be energy inefficient. That problem is compounded by the fact conventional computers were originally designed for scientific computation but not ANN or machine learning algorithms.
Using memristors to execute ANNs more closely mimics the working mechanisms in the brain; they remember the level of resistance they were tuned to in response to an electrical current even after their power is turned off. The computation will also happen on the memristor devices in situ. This saves the step of shuttling data back and forth to the chip.
But remembering isn’t quite the same as learning, said Chen.
“Before the second paper was written, we were not training the neural network on the chip itself,” explained Chen. “We had to precisely calculate parameters on traditional computers and then program the computed parameters to the memristor devices. We could give it parameters representing a cat, for example, and it could accurately memorize the parameters and recognize that exact cat later.”
Working out the necessary parameters and tuning the memristor to the corresponding state was time-consuming and inefficient, though. And, at the end of the day, the chip was not learning what makes a cat, a cat. It was simply memorizing an iteration of a cat.
The mixed-signal training acceleration framework that Chen and his collaborators proposed in 2014 realized the idea of self-training in the neural network using a sophisticated mixed-signal circuit. “The second paper closed the loop, allowing the neural network to both memorize and learn on the chip,” said Chen. “That’s why these two papers together are foundational.”
Since the paper’s publication in 2014, work in AI chips—also called machine learning accelerators— has become an immensely popular field. The research focus grew in popularity to comprise an entirely new track at many hardware conferences. And interest extends beyond the research labs of academic institutions like Duke.
“Memristor-based AI Chips’ high energy efficiency and large computing capacity are promising to power-hungry large-scale applications like large language models (LLMs),” said Chen. “There are many new startups and a lot of investment in developing the technology.”