Chen Wins IEEE Donald O. Pederson Best Paper Award

As semiconductor companies continue pushing to make computer processing chips smaller and faster, there is a never-ending number of hurdles to overcome. In recent years, one of those challenges has been so-called “lithography hotspots” in the manufacturing process that can cause defects, wasting millions of dollars in time, effort and materials.

All modern semiconductor manufacturers use photolithography to create the minuscule designs of transistors, circuits and other features required for their processors. This entails projecting light through a patterned mask onto a wafer coated with photoresist. The exposure changes the photoresist so selected regions can be removed, creating a patterned guide for later etching, deposition or implantation steps.

Given the incredibly small feature sizes and incredibly complex patterns used by today’s advanced semiconductor industry, it comes as no surprise that sometimes the designs have flaws. One issue is that certain layout patterns are difficult to print accurately, creating locations where features may bridge together or pinch apart during lithography. These vulnerable layout locations are called lithography hotspots.

Identifying layout patterns in the various designs that end up causing these hotspots sounds like a perfect application for machine learning. And it is. The problem with trying to use machine learning to fix these problems, however, is that it needs a lot of data to work—more data than any individual company typically has at its disposal.

Then there’s the problem of intellectual property.

“Sharing those data can violate intellectual property concerns,” explained Yiran Chen, the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University. “We wanted to find a way for companies to learn together while still protecting their data.”

Solving this conundrum is the topic of a paper published by Chen’s laboratory. Titled “Lithography Hotspot Detection Based on Heterogeneous Federated Learning with Local Adaptation and Feature Selection,” the paper was recently chosen for the IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award.

The award recognizes the best paper published in Transactions on Computer-Aided Design of Integrated Circuits and Systems publication within the past two years. It is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research.

“Our paper tackles the problem of using machine learning to detect potential manufacturing defects before they actually happen,” said Jingyu Pan, the first author of the paper, who recently received his PhD from Chen’s lab and is now working at Nvidia. “This allows companies to fix the problem before fabrication or costly late-stage redesign.”

The paper outlines a method for multiple chip design companies to collaboratively train a machine learning model for lithography hotspot detection without giving away any of their intellectual property. Instead of sending sensitive layout patterns to a shared database, each company trains the model privately on its own data and shares only model updates, allowing companies to collaborate without exposing their proprietary layouts. The shared global model captures common hotspot-detection knowledge across companies, while each company keeps a local component that adapts the detector to its own proprietary layout patterns.

While this may sound like a straightforward solution, it is easier said than done. Given the wide variety of circuit topologies and thus layout patterns used by different design companies, training a model in this collaborative fashion is difficult. And it becomes even more difficult when the results must be customized back to a specific design. “This approach creates a model from the generalizable patterns in the collaboration while still keeping flexibility for each company to adapt a unique local sub-model to its own proprietary layout data,” said Chen.