Hai "Helen" Li

Clare Boothe Luce Associate Professor in Electrical and Computer Engineering

Research Interests:
Brain-inspired computing systems, neuromorphic design
Memory design and architecture based on conventional and emerging technologies
Device/circuit/architecture co-design for low power and high performance

Appointments and Affiliations

• Associate Professor in the Department of Electrical and Computer Engineering
• Associate Professor of Computer Science

Contact Information

• Office Location: Rm103 Hudson Hall, 100 Science Dr., Durham, NC 27701
• Office Phone: (919) 660-1373
• Email Address: hai.li@duke.edu
• Websites:
  • Google Scholar
  • Personal page

Education

• Ph.D. Purdue University, 2004

Research Interests

Research Interests: Brain-inspired computing systems and neuromorphic design, memory design and architecture based on conventional and emerging technologies, and device/circuit/architecture co-design for low power and high performance.

Awards, Honors, and Distinctions

• Best Paper Award for the paper titled “Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses”. Asia and South Pacific Design Automation Conference (ASPDAC). 2017
• Fulton C. Noss Faculty Fellow. University of Pittsburgh. 2016
• Best Paper Award for the paper titled “Quantitative Modeling of Racetrack Memory - A Tradeoff among Area, Performance, and Power”. Asia and South Pacific Design Automation Conference (ASPDAC). 2015
• Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2015
• Best Paper Award for the paper titled “A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2014
• Best Paper Award for the paper titled “Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems”. Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI). 2013
• Air Force Visiting Faculty Research Program (VFRP) Fellowship. AFRL/RIB. 2013
• DARPA Young Faculty Award. Defense Advanced Research Projects Agency (DARPA). 2013
• NSF Career Award. National Science Foundation (NSF). 2012
• Air Force Summer Faculty Fellowship Program Award (AF-SFFP). AFRL/RITC. 2011
• Best Paper Award for the paper titled “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM”. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED). 2010
• Best Paper Award for the paper titled “Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)”. the 9th International Symposium on Quality Electronic Design (ISQED). 2008

Courses Taught

• COMPSCI 350L: Digital Systems
• ECE 350L: Digital Systems
• ECE 550D: Fundamentals of Computer Systems and Engineering
• ECE 590: Advanced Topics in Electrical and Computer Engineering
• ECE 891: Internship
• ECE 899: Special Readings in Electrical Engineering

In the News

• Hai Helen Li: New Pratt Professor Models the Future of Computing After the Human Brain (Jan 3, 2017)

Representative Publications

• Wang, D; Ma, L; Zhang, M; An, J; Li, HH; Chen, Y, Shift-Optimized Energy-Efficient Racetrack-Based Main Memory, Journal of Circuits, Systems and Computers, vol 27 no. 05 (2018), pp. 1850081-1850081 [10.1142/S0218126618500810] [abs].
• Basu, A; Acharya, J; Karnik, T; Liu, H; Li, H; Seo, J-S; Song, C, Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions, Ieee Journal on Emerging and Selected Topics in Circuits and Systems, vol 8 no. 1 (2018), pp. 6-27 [10.1109/JETCAS.2018.2816339] [abs].
• Mao, M; Wen, W; Zhang, Y; Chen, Y; Li, H, An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory, Ieee Transactions on Computers, vol 66 no. 9 (2017), pp. 1478-1490 [10.1109/TC.2017.2690855] [abs].
• Hu, M; Chen, Y; Yang, JJ; Wang, Y; Li, HH, A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks, Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, vol 36 no. 8 (2017), pp. 1353-1366 [10.1109/TCAD.2016.2618866] [abs].
• Guo, J; Wen, W; Hu, J; Wang, D; Li, H; Chen, Y, FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency, Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, vol 36 no. 7 (2017), pp. 1167-1180 [10.1109/TCAD.2016.2619480] [abs].