Memory Schedulers: Taking the CPU Side
Friday, November 13, 2015
12:00 pm - 1:00 pm
Social Sciences 119
Prof. José Martínez, Cornell University
There's a plethora of publications over the last decade on making a memory controller's scheduling decisions smarter. As DRAM frequencies continue to increase relative to processor speed, however, it becomes harder to design a sophisticated memory scheduler that may fit in the controller's tight clock cycle. In this presentation I will argue that it may make more sense to shift the analysis of load instructions to the CPU side: By providing pre-digested information about loads from the CPU to the memory schedulers, we can make sophisticated memory decisions while maintaining a lean memory controller that can take scheduling actions quickly. Moreover, because the CPU knows more about those loads in the program context than the memory controller, the scheduler's overall scheduling quality may be superior to a local design at the memory controller. I will describe one such design, pairing up a processor-side load criticality predictor with a lean memory controller that prioritizes load requests based on ranking information supplied from the processor side.