ECE Seminar : Template Based High-level and Logic Synthesis with Approximate Computation for Higher and Energy Efficient Computing

Oct 11

Wednesday, October 11, 2017

1:30 pm - 3:00 pm
Fitzpatrick Center Schiciano Auditorium Side A

Presenter

Masahiro Fujita, Professor, VLSI Design and Education Center (VDEC), University of Tokyo

Although FPGA or hardware-based implementation of software can give us not only higher performance but also energy efficient computing, efficient implementation algorithms as hardware and as software can be significantly different. Typical high-level synthesis methods may not concentrate on this issue, as they are targeting general hardware designs. In this talk performance directed synthesis targeting throughput based computations rather than transitional high-level synthesis techniques is proposed based on template-based approaches. With templates, given data flow graphs are automatically converted into the ones for high performance with FPGA implementation by using SAT-based automatic refinement methods. Then we further explore the use of approximate computation to reduce the amount of hardware while keeping the required accuracy. We discuss the proposed techniques from the viewpoints of a couple of case studies, such as neural network simulation and HEVC (High Efficiency Video Coding).

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Contact

Naseree, Alexandra
660-5241
alexandra.naseree@duke.edu