ECE Seminar: Software-Hardware Co-Design for Efficient Neural Network Acceleration

Jan 30

Tuesday, January 30, 2018

1:00 pm - 2:00 pm
TBD

Presenter

Yu Wang, Associate Professor with the Department of Electronic Engineering, Tsinghua University

Artificial neural networks, which dominate artificial intelligence applications such as object recognition and speech recognition, are in evolution. To apply neural networks to wider applications, customized hardware are necessary since CPU and GPU are not efficient enough. FPGA can be an ideal platform for neural network acceleration (inference part) since it is programmable and can achieve much higher energy efficiency compared with general-purpose processors. However, the long development period and insufficient performance of traditional FPGA acceleration prevent it from wide utilization. Firstly, we will review the current deep learning acceleration work together with the chart we make, and then review our solution: a complete design flow to achieve both fast deployment and high energy efficiency for accelerating neural networks on FPGA [FPGA 16/17]. Deep compression and data quantization are employed to exploit the redundancy in algorithm and reduce both computational and memory complexity. Two architecture designs for CNN and DNN/RNN are proposed together with compilation environment. Evaluated on Xilinx Zynq 7000 and Kintex Ultrascale series FPGA with real-world neural networks, up to 15 times higher energy efficiency can be achieved compared with mobile GPU and desktop GPU. We will further introduce our effort on how to turn these papers into production from Deephi Tech's perspective, i.e. what we achieved for more test cases.

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Contact

Aleksandrova, Olena
919-660-5252
opa@duke.edu