Computer Systems and Engineering Seminar: Use it or Lose it: Wearout and Lifetime in Future Chip-Multiprocessors
Monday, January 27, 2014
1:30 pm - 2:45 pm
Hudson Hall 222
Moore's Law scaling is continuing to lead to today's multicore Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Deep submicron CMOS process technology is marred by increasing susceptibility to wearout. Prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic for the system, a single fault in the inter-processor Network-on-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this talk, I develop critical path models for HCI-and NBTI-induced wear due to the actual stresses caused by real workloads, applied onto the interconnect microarchitecture. A key finding from this modeling being that wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. A novel wearout decelerating scheme is then developed in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption.